1. Field of the Invention
The present invention relates generally to systems and methods for designing synchronous digital circuits, and specifically to designing a skew-tolerant true-single-phase clocking flip-flop.
2. Background and Objects of the Present Invention
Clock signals are used in synchronous digital circuits to allow different parts of the circuit to communicate with each other without data loss. Values carried by data signals are defined at specific times relative to the transitions of the clock signals, and are read into and out of storage elements at times related to these same transitions. The clock signals are typically distributed to all storage elements in the design. The inevitable signal delay caused by the distribution network must be taken into account during its design, such that the clock signal arrives at all storage elements at substantially the same time.
The required degree of simultaneity may be quantified with the setup time and hold time for the clocked devices, such as flip-flops. In order to meet the required setup time for a flip-flop device, input data must be present at the data input lead of the flip-flop device and in stable form for a predetermined amount of time before the clock transition. In order to meet the hold time requirement for the flip-flop device, the data must be stable from the time of the clock transition on arrival at the control lead of the flip-flop up to a certain time interval after the arrival of the clock.
Many setup time violations may be remedied simply by slowing down the frequency at which the design is clocked. However, hold time violations may be caused by clock skew, and can persist regardless of the clock frequency. Insufficient control of the clock delay in different parts of the clock distribution network may cause the clock edges to arrive at the clocked devices at different times. These time differences constitute the clock skew, which, if large enough to cause hold violations (or setup violations if the clock frequency is high enough), can cause circuit malfunction. For example, the clock skew may cause data in a first register to shift earlier than data on a second register. The hold time requirement of the second register may, therefore, be violated, and data bits may then be lost.
A dominant clocking strategy presently used for digital circuits is single-phase clocking with true-single-phase-clocking (TSPC) flip-flops. Single-phase clocking systems use only one clock signal, and therefore, only one clock distribution network, which avoids the task of controlling clock skew among several networks. The only clock skew present in a single-phase-clocking system is that created among several instances of the same signal which have suffered different amounts of delay through different paths in the distribution network. Therefore, the simplified clock skew management task in single-phase-clocking systems allows for high clock frequencies compared with previously utilized clocking techniques. These benefits often outweigh the drawbacks, one of which is a stringent requirement on the clock transition speed.
Current schemes for distributing clock signals to storage elements concentrate on ensuring synchronicity of all clock signals. Clocks are typically distributed in a tree-like structure, whereby delays in different branches can be balanced to a high degree. The highly balanced clock trees traditionally used with single-phase clocking cause all TSPC flip-flops in the design to toggle virtually simultaneously. The capacitive loads driven by the flip-flop outputs are then charged simultaneously, drawing a large current spike from the supply.
Such current spikes are undesirable due to the resulting metal migration in supply wires. The rate of migration depends strongly upon the maximum current density that occurs in the wire. Large current spikes thus require wider supply wires with the concomitant cost in area. In addition, large current spikes feature large values of dI/dt. Together with the parasitic inductance present in the IC package, the current spikes thus cause voltage fluctuations on the supply lines. These fluctuations can cause both malfunction of the digital circuits and reduced performance level of co-located analog circuity. Although the aforementioned problems may be corrected by advanced packaging and on-chip decoupling capacitance, both of these methods increase the cost of the device. Furthermore, the large current spikes themselves can couple inductively into other parts of the design and cause malfunction or performance reduction. The aforementioned electrical problems can potentially be alleviated by introducing a controlled amount of clock skew, such that not all storage elements change value at the same time. However, such purposefully added skew could create logical malfunctions due to hold violations, as described above.
It is, therefore, an object of the present invention to provide a skew-tolerant TSPC flip-flop that reduces the overall current spike.
A preferred embodiment of the present invention is directed to a skew-tolerant TSPC flip-flop that reduces the overall current spike by allowing willful introduction of skew in the clock tree of a single-phase design. More precisely, a split-clock TSPC flip-flop, which allows the flip-flop hold times to be met even with skewed clocks, can be substituted for a traditional TSPC flip-flop in a sequential logic circuit. By introducing clock skew, different flip-flops toggle at slightly different times, such that the corresponding current spikes are slightly staggered in time. Therefore, the clock skew can serve to xe2x80x9csmear outxe2x80x9d the overall current spike, which reduces the maximum value of the current spike as well as the maximum value of dI/dt. The input of the split-clock TSPC flip-flop can be latched according to a first clock signal, which was used in a preceding stage, while the output of the split-clock TSPC flip-flop can be driven according to a second clock signal. The first and second clock signals are skewed in time, but have the same frequency and substantially the same phase. In one embodiment, an additional Metal Oxide Semiconductor (MOS) device can be included within the split-clock TSPC flip-flop to reduce power dissipation in cases of large clock skew.